1. Technical Field of the Invention
This invention relates to phase error detection. More specifically, it relates to the detection of phase errors between different clock domains in application specific integrated circuit chips (ASICs).
2. Background Art
Clock phase alignment errors can occur in any application specific integrated circuit (ASIC) chip which employs multiple clocks running synchronously at different frequencies. Examples of such chips include microprocessors with high frequency internal clocks and slower bus interface clocks, memory controller chips with one clock frequency for a system bus and another clock frequency for a dedicated memory bus, and I/O bridge chips which communicate with multiple buses running at different frequencies.
Synchronous communications between any two clock domains requires that the phase relationship between the clocks remain constant. A phase alignment error exists when the phase relationship between two synchronous domains does not remain constant, or is not initialized to the alignment for which the cross domain circuitry is designed. This error condition results in incorrect and missing data during communications between clock domains and consequently causes multiple secondary error effects. Since existing error checking mechanisms are unable to detect phase alignment errors, one or more of the secondary errors is perceived to be a primary error. In a customer environment this results in incorrect failure isolation and unnecessary replacement of parts. In a lab bring up environment it becomes necessary to spend extra time attaching fast oscilloscopes to systems under test when phase alignment errors are suspected.
A particular memory and I/O controller chip, for example, communicates with processors, external memory, and I/O devices. The internal circuits of this chip are partitioned into multiple clock domains which operate at frequencies that match the associated external devices. In this specific example, internal circuits are divided into three clock domains: a processor clock domain, a memory clock domain, and an I/O clock domain. In order to minimize latencies and improve system performance, the memory and processor clock domains inside the chip operate synchronously at a frequency ratio of 2:3. Consequently, the chip is susceptible to phase alignment errors either as a result of circuit failure or incorrect phase locked loop (PLL) initialization.
Referring to FIG. 1, the correct phase relationship at a synchronous 2:3 frequency ratio is illustrated.
It is an object of the invention to provide a circuit for detecting clock phase alignment errors.
It is a further object of the invention to provide for correct failure isolation.
It is a further object of the invention to detect phase alignment errors in an ASIC, such as those arising from circuit failure or incorrect PLL initialization.
It is a further object of the invention to detect incorrect clock phase alignment between synchronous clock domains by using fully synchronous signals and not requiring sampling rates in excess of the clock frequencies in either of the two domains being monitored.
It is a further object of the invention to detect incorrect clock phase alignment between synchronous clock domains with detection circuitry which performs accurately over the same process range that the rest of the chip is designed to meet, and do so without placing special requirements on logic synthesis and timing tools, without custom design techniques, and without embedded analog circuits.